The present invention relates to a semiconductor memory cell of a large capacity having a redundancy circuit.
A redundancy circuit is now widely used in a memory device of a large capacity such as dynamic RAMs (hereinafter called DRAM) to improve the production yield.
A redundancy circuit includes additional spare memory cells and a spare decoder/word-driver for selecting a spare memory cell, which are used when a part of the ordinary memory cells is found to be defective.
If a designated address corresponds to a defective memory cell in a semiconductor memory device having a redundancy circuit of this type, a decoder and a spare decoder are activated to select a word line or a spare word line. A decoder inhibit signal is generated by the spare decoder so as not to select a word line, and a word line drive signal is generated by a word line driver to drive a spare word line. In this case, in order to prevent destruction of cell data, it is important to supply a word line drive signal only after a decoder output has become definite. In view of this, also a word line activation signal is supplied after the decoder output has become definite.
However, all of the bits in a semiconductor memory device having a redundancy circuit often operate normally, so that it becomes unnecessary to use the redundancy circuit. In such a case, the normal decoder output "H" level is not replaced with "L" level, but the timing of outputting a word line activation signal WA is delayed by a time t.sub.inh irrespective of whether this signal can be supplied if once the normal decoder output is determined as the "H" level. The reason for this is that the timing is set on the assumption that a spare word line may be selected under any conditions. The time t.sub.inh is the period from the instant when the normal decoder output is determined to the instant when the normal decoder output assumes the "L" level to use the spare circuit. In other words, the access time is delayed by time t.sub.inh.
The access delay due to the redundancy circuit presents a serious overhead of a high speed, large capacity memory, particularly DRAMs, in terms of high speed performance.
In a conventional semiconductor memory device having a redundancy circuit, the operation timings are determined on the assumption that the redundancy circuit will always be used, to thereby pose the problem of access delay when the redundancy circuit is not used.